Regviz

NXP Semiconductors /QN908XC /BLEDP /FREQ_DOMAIN_CTRL5

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FREQ_DOMAIN_CTRL5

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/QN908XC/BLEDP/FREQ_DOMAIN_CTRL5#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0GAIN_TED 0SYNC_DIN_SAT_VALUE 0 (SYNC_DIN_SAT_EN)SYNC_DIN_SAT_EN 0CNT_SETTLE_IDX 0TRIG_XCORR_CNT 0XCORR_RSSI_TH3 0XCORR_RSSI_TH2 0XCORR_RSSI_TH1 0XCORR_RSSI_TH0

Description

frequency domain control register 5

Fields

GAIN_TED

ted gain
SYNC_DIN_SAT_VALUE

<u 1 2>sync din amplitude limit value 0 to 1.75 correspond to 2 to 3.75
SYNC_DIN_SAT_EN

sync din amplitude limit enable
CNT_SETTLE_IDX

buffer settle threshold from 32 to 256 step is 32
TRIG_XCORR_CNT

correlation search window size.
XCORR_RSSI_TH3

xcorr triger rssi threshold0
XCORR_RSSI_TH2

xcorr triger rssi threshold0
XCORR_RSSI_TH1

xcorr triger rssi threshold0
XCORR_RSSI_TH0

xcorr triger rssi threshold0

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data